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Developer Divyansh Agrawal reports that Qwenputer, an experimental model based on Qwen3.5 4B, can run a compiled 32-bit RISC-V CPU within the model’s forward passes. The CPU uses Gated DeltaNet state as addressable memory; Agrawal says it passed official RISC-V tests and completed an 18-million-instruction run without error. The report is a creator’s account, and independent verification and performance details are not provided in the supplied material.
Developer Divyansh Agrawal says he has built Qwenputer, an experimental version of Qwen3.5 4B that runs a 32-bit RISC-V processor inside the model’s forward passes. The design uses the model’s Gated DeltaNet state as addressable memory, allowing it to execute arithmetic and code without calling an external computing tool or runtime, according to Agrawal’s report.
Agrawal describes Qwenputer as a stock Qwen3.5 4B model with additional compiled weights. The CPU is specified as RV32IM, with the Zba extension and a small unit for larger-number arithmetic. It occupies 11 layers added ahead of Qwen’s 32, while the original model weights are said to remain unchanged. The report says no training was needed: a compiler maps the CPU’s circuit operations into model weights.
For memory, the experiment configures Gated DeltaNet heads so they can store and retrieve exact values. Agrawal says setting the gate to one prevents stored state from fading, while a write strength of one replaces a value; one-hot keys then select individual rows for writing or reading. These rows hold CPU information such as registers, memory, and the program counter.
The CPU runs as Qwen generates a sequence of tokens that records its instructions and state changes. Agrawal says the model can run C and MicroPython programs this way, though execution is slow. A small driver, RvChat, loads firmware into the DeltaNet state and keeps the CPU trace tokens out of Qwen’s layers. The report says the model uses a familiar tool-call format to communicate with the internal processor, but does not make an external tool call.
A CPU Built From Model State
Qwenputer is a demonstration of a different way to combine language models and computation: rather than asking a separate software tool to execute instructions, it represents a processor and its memory within a model’s learned computation. If the reported behavior holds up to independent testing, it could help researchers explore reliable computation inside neural networks and ways to connect learned systems to exact operations.
The result should not be confused with a general-purpose computer embedded in a model. Agrawal says the CPU is not a Linux-class system, and that running code is slow. The report establishes a technical experiment, not a practical replacement for ordinary processors or external execution environments.
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How DeltaNet Holds Memory
Qwen3.5 uses a hybrid architecture. Agrawal says three of every four attention layers use Gated DeltaNet, a recurrent mechanism that maintains a state matrix as tokens are processed. In ordinary use, that state is part of the model’s processing; Qwenputer’s central modification makes selected state rows behave like exact, addressable memory for a CPU.
The broader idea of delta-rule networks acting as associative memory predates this project. Agrawal cites a 2021 paper by Imanol Schlag, Kazuki Irie and Jürgen Schmidhuber on linear transformers and fast-weight programming. He presents Qwenputer’s contribution as turning that type of memory into an exact, addressable structure capable of supporting a complete processor within a production model’s layers.
“The CPU runs completely within the forward passes of the model.”
— Divyansh Agrawal, Qwenputer’s creator
Independent Testing Is Not Provided
The performance and test results in the supplied material come from Agrawal’s own report. It does not provide independent replication, detailed timing or throughput measurements, or an outside assessment of the implementation. The 18-million-instruction figure is described as a free-running test, but the report excerpt does not give enough detail to evaluate its workload or testing conditions.
It is also unclear how the approach performs across a wider range of programs, how much computation the added layers require, or whether the design can be adapted to other model sizes and architectures. The report describes an experimental model and does not establish that standard Qwen3.5 deployments can run the CPU without the added weights and driver.
Code and Model for Review
Agrawal says Qwenputer’s model is available through Hugging Face and ModelScope, with code on GitHub. Those releases give other developers a way to inspect the implementation and test the reported behavior. No further milestone or independent benchmark is specified in the supplied report; follow-up evaluation would be needed to establish reproducibility, speed, and the range of programs it can support.
Key Questions
What is Qwenputer?
It is an experimental model based on Qwen3.5 4B, with additional weights that implement a RISC-V CPU inside the model’s forward passes, according to its creator.
Does it use an external processor or tool?
Agrawal says the CPU runs within the model and does not rely on an external tool call or runtime. A small driver loads firmware into the model’s state.
How does the model provide the CPU with memory?
The project configures Gated DeltaNet state to store and retrieve exact values in selected rows, which serve as memory for CPU data.
Has the CPU’s performance been independently verified?
The supplied report gives test claims from the creator, including passing RISC-V tests and an 18-million-instruction run. It does not provide independent verification or detailed performance measurements.
Can Qwenputer run ordinary computer programs?
Agrawal says it can run C and MicroPython, but describes execution as slow and says the processor is not a Linux-class system.
Source: divagr.com
